
2011 Microchip Technology Inc.
DS39931D-page 127
PIC18F46J50 FAMILY
REGISTER 9-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h)
R/W-1
OSCFIP
CM2IP
CM1IP
USBIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIP:
Oscillator Fail Interrupt Priority bit
1
=High priority
0
= Low priority
bit 6
CM2IP:
Comparator 2 Interrupt Priority bit
1
=High priority
0
= Low priority
bit 5
C12IP:
Comparator 1 Interrupt Priority bit
1
=High priority
0
= Low priority
bit 4
USBIP:
USB Interrupt Priority bit
1
=High priority
0
= Low priority
bit 3
BCL1IP:
Bus Collision Interrupt Priority bit (MSSP1 module)
1
=High priority
0
= Low priority
bit 2
HLVDIP:
High/Low-Voltage Detect Interrupt Priority bit
1
=High priority
0
= Low priority
bit 1
TMR3IP:
TMR3 Overflow Interrupt Priority bit
1
=High priority
0
= Low priority
bit 0
CCP2IP:
ECCP2 Interrupt Priority bit
1
=High priority
0
= Low priority